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A time-domain latch interpolation technique for low power flash ADCs | Semantic Scholar
Simplified schematic of the interpolating flash ADC. Figure 4.... | Download Scientific Diagram
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Complete synoptic of the 8 bits flash ADC with interpolation and QV... | Download Scientific Diagram
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PDF) A 6 bit 25 GS/s flash interpolating ADC in 90 nm CMOS technology
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A 6-b 4.1-GS/s Flash ADC With Time-Domain Latch Interpolation in 90-nm CMOS
JLPEA | Free Full-Text | Review of Analog-To-Digital Conversion Characteristics and Design Considerations for the Creation of Power-Efficient Hybrid Data Converters | HTML
Complete synoptic of the 8 bits flash ADC with interpolation and QV... | Download Scientific Diagram
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Figure 3 from A 1.2 V 7-bit 1 GS/s CMOS Flash ADC with Cascaded Voting and Offset Calibration | Semantic Scholar
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A time-domain latch interpolation technique for low power flash ADCs | Semantic Scholar